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Integrated Circuit Systems, Inc.
ICS9178-03
245 MHz Clock Generator and Integrated Buffer for PowerPC
General Description
The ICS9178-03 generates all clocks required for high speed PowerPC RISC microprocessor systems. Generating clocks in phase with an external reference frequency allows the ICS9178-03 to be used as a multiplying zero delay buffer. Three different multiplying factors are externally selectable. These factors can be customized for specific applications. An external frequency can be directly applied to aid system testing. With 2X processor clock speeds up to 245 MHz, PECL outputs are provided. User selectable frequency ratios are available for PCLK/BCLK and PCLK/XCLK. Each pair of clocks outputs have separate supply pins to minimize output jitter and allow them to operate at 5V, 3.3V or custom voltage levels.
Features
Generates 2 PECL 2x processor, 2 TTL/CMOS 1x processor and 10 selectable bus clocks 2XPCLK ranges from 75 MHz to 245 MHz (5V or 5V/3.3V mixed supply) or 60 to 170 MHz (3.3V only) Asymmetric duty cycle bus clock for PowerPC Bus to processor clock skews less than 250ps 2XPCLK to PCLK skew controlled at 300 300ps Selectable reference multiplying factors Selectable PCLK/BCLK and PCLK/XCLK ratios Separate supplies allow 5V and 3.3V output mix 3.0V - 5.5V supply range 44-pin PQFP package
Applications
Ideal for high-speed systems based on PowerPC
Block Diagram
PowerPC is a trademark of Motorola Corporation.
ICS9178-03 Rev C 02/12/98P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9178-03
Pin Configuration
X_S1 0 0 1 1
X_S0 0 1 0 1
XCLK_(0,1) PCLK BCLK DCLK Tristate
_=A,B,C
44-Pin PQFP
Functionality
FS1 0 0 1 1 X 0 0 1 1 FS0 0 1 0 1 X 0 1 0 1 RST 1 1 1 1 0 1 1 1 1 TEN 0 0 0 0 X 1 1 1 1 *VCO 6x REF 8x REF 4x REF X X TCLK TCLK TCLK TCLK 2XPCLK VCO VCO VCO 1 0 TCLK TCLK TCLK TCLK PCLK VCO/2 VCO/2 VCO/2 1 0 TCLK/2 TCLK/2 TCLK/2 TCLK/2 ABCLK (H/L%) VCO/6 (66/33) VCO/8 (75/25) VCO/12 (50/50) 1 0 TCLK/6 (66/33) TCLK/8 (75/25) TCLK/12 ( 66/33) TCLK/2 BCLK VCO/6 VCO/8 VCO/4 1 0 TCLK/6 TCLK/8 TCLK/12 TCLK/2 DCLK VCO/4 VCO/4 VCO/4 1 0 TCLK/4 TCLK/4 TCLK/4 TCLK/4
*VCO range is limited from 75- 245 MHz at 5V 5% and 60 - 170 MHz at 3.3V 5%. Divide ratios assume BCLK is externally fed back to FBCLK. The 2XPCLK series or Thevinen trace terminations must be optimized for the specific operating frequency and board layout. The rising edge of ABCLK is coincident with the rising edges of 2XPCLK, PCLK and other BCLKs.
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ICS9178-03
Pin Description
PIN NUMBER 32 31 6 5 30 29 3 2 1 4 44 43 42 41 28 27 11 10 8 7 22 21 24 23 20 38* 37* 36 35 25 26 19 16 17 15 14 13 12 18 40 39 9 33 34 PIN NAME XAS0 XAS1 XCLKA0 XCLKA1 XBS0 XBS1 XCLKB0 XCLKB1 VDDXBA GNDXBA GNDXC XCLKC0 XCLKC1 VDDXC XCS0 XCS1 PCLK0 PCLK1 GNDP VDDP 2XPCLK0 2XPCLK1 EVDD EGND EGND FS0 FS1 FBCLK REFCLK AVDD AGND DCLK VDDD GNDD BCLK0 BCLK1 GNDBAB VDDBAB ABCLK TCLK TEN# RESET# VDD GND TYPE Input Input Output Output Input Input Output Output -- -- -- Output Output -- Input Input Output Output -- -- Output Output -- -- -- Input Input Input Input -- -- Output -- -- Output Output -- -- Output Input Input Input -- -- DESCRIPTION LSB Programmable Group A frequency selector. MSB Programmable Group A frequency selector. TTL/CMOS group A programmable clock output. TTL/CMOS group A programmable clock output. LSB Programmable Group B frequency selector. MSB Programmable Group B frequency selector. TTL/CMOS Group B programmable clock output. TTL/CMOS Group B programmable clock output. Power for programmable Group A and B buffers (Pins 2, 3, 5, 6). Ground for programmable Group A and B buffers (Pins 2, 3, 5, 6). Ground for the programmable Group C buffers (Pins 42 and 43). TTL/CMOS Group C programmable clock output. TTL/CMOS Group C programmable clock output. Power for the XC signal output buffers (Pins 42 and 43). LSB Programmable Group C frequency selector. MSB Programmable Group C frequency selector. TTL/CMOS 1X Processor clock output. TTL/CMOS 1X Processor clock output. Ground for PCLK output buffers (Pins 11 and 10). Power for PCLK output buffers (Pins 11 and 10). PECL 2X Processor clock output. PECL 2X Processor clock output. Power for PECL buffers (Pins 21 and 22). Ground for PECL buffers (Pins 21 and 22). Ground for PECL buffers (Pins 21 and 22). LSB frequency select PLL (divider mode control). MSB frequency select PLL (divider mode control). External PLL feedback path from one of the BCLK outputs. External reference clock input. Power for the analog PLL circuitry. Ground for the analog PLL circuitry. TTL/CMOS D clock output. Power for D output buffers (Pin 19). Ground for D output buffer (Pin 19). TTL/CMOS B (Bus) clock output. TTL/CMOS B (Bus) clock output. Ground for output buffers AB and B clocks (Pins 14, 15 & 18). Power for output buffers AB and B clocks (Pins 14, 15 & 18). TTL/CMOS AB Bus clock (has Asymmetric duty cycle). External test clock input. Test enable (tie low). Sync register reset (active low). Digital power supply for 5.0 or 3.3V. Digital ground supply.
*=Pin is pulled-up to VDD internally by the device. 3
ICS9178-03
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics
Device Specifications
Maximum Ratings DESCRIPTION Supply voltage relative to GND Input voltage with respect to GND Operating temperature Storage temperature Max soldering temperature (10 sec) Junction temperature Package power dissipation SYMBOL VDD VIN TOPER TSTOR TSOL Tj PDISS 800 MIN -0.5 -0.5 0 -65 MAX 7.0 VDD +0.5 +70 +150 +260 +135 900 UNITS V V C C C C mWatts
DC Characteristics
PARAMETER High level input voltage Low level input voltage High level CMOS output voltage Low level CMOS output voltage High level PECL output voltage (2XPCLK) (Note 1) Low level PECL output voltage (2XPCLK) (Note 1) Input high current
VDD =+5V 5%, 0C TAMBIENT +70C unless otherwise stated
SYMBOL VIH VIL VOH VOL VOHP VOLP IIH IIL1 IIL2 IOZ IDD IDD-TYP CIN IOH=-25mA IOL=25mA 110 ohm load to ground 110 ohm load to ground VIH=VDD VIL=0V VIL=0V (tristate) @240 MHz on 2XPCLK @75 MHz on 2XPCLK -10 -10 145 80 -10 1.9 2.2 0.3 0.5 10 -150 10 10 185 100 8 2.4 0.4 TEST CONDITIONS MIN 2.0 0.8 TYP MAX UNITS V V V V V V A A A A mA mA pF
Input low current (MSX pins, pull-up) Input low current (other inputs) Output leakage current (XCLKs) Power supply current Power supply current (typical) (Note 1) Input capacitance (Note 1)
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
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ICS9178-03
AC Characteristics
VDD =+5V 5%, 0C TAMBIENT +70C unless otherwise stated
PARAMETER Input Frequency (Note 1) Input Clock Rise time (Note 1) Input Clock Fall time (Note 1) Output Frequency (2XPCLK) Output Rise time, 0.8 to 2.0V 20% to 80% (Note 1) Fall time 2.0 to 0.8 80% to 20% (Note 1) Output Rise time 80% to 20% (Note 1) Output Fall time 80% to 20% (Note 1) Duty cycle 2XPCLK (Note 1) Pulse Width, High, 2XPCLK (Note 1, 2) Pulse Width, Low, 2XPCLK (Note 1, 2) Duty cycle ABCLK (Note 1) Duty cycle ABCLK (Note 1) Duty cycle TTL (other clocks) (Note 1) Jitter 1 Sigma 2XPCLK (10,000 samples) (Note 1) Jitter 1 Sigma 1XPCLK B & D (10,000 samples) (Note 1) Jitter 1 Sigma AB clock (10,000 samples) (Note 1) Jitter Absolute 2XPCLK (Note 1) Jitter Absolute 1XPCLK, B, D clocks (Note 1) Jitter Absolute AB clock (Note 1) SYMBOL fi ICLKr ICLKf fo2XPCLK 6X mode, 8X mode 4X mode tr2XPCLK tf2XPCLK 15pF load 15pF load 0.8 to 2.0V 20% to 80% 2.0 to 0.8V 80% to 20% t(TTL)r t(TTL)f dt1 Tpwr Tpwr dt3 dt4 15pF load 15pF load 200 to 240 MHz @ 1.4V 110 ohm, 15pF load @ 1.8V, 110Load 2 @ 0.6V, 110Load 2 15pF load @ 1.4V (8X mode) 15pF load @ 1.4V 6X mode 15pF load @ 1.4V 4X mode dt5 Tj1s1 Tj1s2 Tj1s3 Tjabs1 Tjabs2 Tjabs3 15pF load @ 1.4V for 200 to 240 MHz on 2XPCLK for 200 to 240 MHz on 2XPCLK for 200 to 240 MHz on 2XPCLK for 200 to 240 MHz on 2XPCLK for 200 to 240 MHz on 2XPCLK for 200 to 240 MHz on 2XPCLK 42.5 1.2 1.0 70 61 45 45 -150 -200 -250 50 75 66 50 50 40 50 60 80 110 120 TEST CONDITIONS MIN 8 75 75 TYP 40.0 MAX 50.0 3 3 245 240 1.0 1.5 1.0 1.5 3.0 2.0 57.5 80 71 55 55 +150 +200 +250 % ps ps ps ps ps ps ns ns % ns ns % % ns ns UNITS MHz ns ns MHz
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production. Note 2: For 70 Load, 2XPCLK level may be pulled-up with a 390 resistor to meet minimum pulse width requirements at both 1.8V and 0.6V at 240 MHz.
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ICS9178-03
AC Characteristics (continued)
VDD =+5V 5%, 0C TAMBIENT +70C unless otherwise stated
PARAMETER Jitter Absolute 2XPCLK (Note 1) Jitter Absolute 1XPCLK, B, D clocks (Note 1) Jitter Absolute 2XPCLK (Note 1) Jitter Absolute 1XPCLK (Note 1) Jitter Absolute AB clock (Note 1) Skew, output to output (P, B, D , AB abd XCLKs) (Note 1) Skew, 2XPCLK to PCLK (2XPCLK is earlier than PCLK) (Note 1) Skew, 2XPCLK to REFCLK (2XPCLK is earlier) (Note 1) Skew, 2XPCLK to DCLK (Notes 1,3) SYMBOL Tjabs4 TEST CONDITIONS for 200 to 240 MHz on 2XPCLK at VDD 4.9 to 5.2V for 200 to 240 MHz on 2XPCLK at VDD 4.9 to 5.2V for < 200 MHz on 2XPCLK for < 200 MHz on 2XPCLK for < 200 MHz on 2XPCLK @ 1.4V @ 1.4V for 240 MHz on 2XPCLK @ 1.4V @ 1.4V MIN -125 TYP 80 MAX +125 UNITS ps
Tjabs5 Tjabs6 Tjabs7 Tjabs8 Tskew1 Tskew2 Tskew3 Tskew4
-160 -200 -250 -300 -250 -600 -600 -600
110 -300 -300 -100
+160 +200 +250 +300 +250 0 0 100
ps ps ps ps ps ps ps ps
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production. Note 2: For 70 Load, 2XPCLK level may be pulled-up with a 390 resistor to meet minimum pulse width requirements at both 1.8Vand 0.6Vat 240 Mhz. Note 3: 2XPCLK is normally earlier than DCLK by up to 600ps and can be later by up to
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ICS9178-03
Applications
PwrPC 601/601+Processor Modules
Frequency Combinations
(XCLK pairs selectable)
SYS BUS F F F 9178 MODE x4 x6 8F 2XPCLK (2XCPU) 4F 6F 8F PCLK(0,1) (CPU) 2F 3F 4F XCLK(0,5) (BUS) 2F, 1F 3F, 1.5F, 1F 4F, 2F, 1F BCLK(0,1) ABCLK 1F 1.5F 2F
PwrPC 601\601+ System Clock Diagram
Frequency Combinations
(selectable SCLK)
OSC F F F 33 33 33 30 30 30 25 25 25 9178 MODE x4 x6 8F x4 x6 x8 x4 x6 x8 x4 x6 x8 2XPCLK (2XCPU) 4F 6F 8F 132 196 264 120 180 240 100 150 200 PCLK (CPU) 2F 3F 4F 66 99 132 60 90 120 50 75 100 XCLK (BUS) 2F, 1F 3F, 1.5F, 1F 4F, 2F, 1F 66, 33 99, 48, 33 132, 66, 33 60, 30 90, 45, 30 120, 60, 30 50, 25 75, 37, 25 100, 50, 25 Q (PCI) 1F 1.5F 2F 33 33 33 30 30 30 25 25 25
PwrPC 603/604 System Clock Diagram
Frequency Combinations
(9178 x4 mode)
OSC F 33 40 33 30 40 33 PwrPC MODE x1, x2 x1, x2 x3 x2, x4 x3 x2, x4 PCLK, DCLK (CPU) 2F, 1F 66, 33 80, 40 -, 33 60, 30 -, 40 66, 33 PwrPC INTERNAL CLOCK 66 80 100 120 120 132 PCLK(0,1) XCLK(0,3) (BUS) 2F, 1F 66, 33 80, 40 66, 33 60, 30 80, 40 66, 33 ABCLK, BCLK(0,1) XCLK(4,5) F 33 PCI) 40 (VL) 33 (PCI) 30 (PCI) 40 (VL) 33 (PCI)
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ICS9178-03
PQFP Package
LEAD COUNT BODY THICKNESS FOOTPRINT (BODY+) DIMENSIONS A A1 A2 D D1 E E1 L e b ccc
44L 2.0 3.20 TOLERANCE MAX. MAX. 0.10 0.25 0.10 0.25 0.10 0.15/-0.10 BASIC +0.05 MAX. 2.45 0.25 2.00 13.20 10.0 13.20 10.0 0.70 0.80 0.35 0.10 0 - 7
Ordering Information ICS9178Y-03
Example:
ICS XXXX- M PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type Device Type (consists of 3 or 4 digit numbers) Prefix
ICS,AV=Standard
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
Y=QFP
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